A new synthesis efficient, high density and high speed ORCA FPGA

Proceedings of CICC 97 - Custom Integrated Circuits Conference Pub Date : 1997-05-05 DOI:10.1109/CICC.1997.606685

S. Singh, B. Britton, C. Spivak, H. Nguyen, W. Leung, B. Andrews, G. Powell, R. Albu, J. He, R. Stuby, M. Chin, Pin-Lin Chiu, J. Steward, Doug Rabold

引用次数: 0

Abstract

This paper describes a new ORCA FPGA that focuses on enhancing the speed and gate density of logic systems implemented using high-level logic synthesis. The new family called ORCA 3C/3T, follows the successful ORCA families: 1C, 2C, 2CA and 2TA. The architecture has been designed for efficiently implementing behavioral-level "functions", in addition to regular digital "logic". It includes Look-Up Tables (LUTs), Flip-Flops (FFs) and a PAL-type decoder block grouped in a twin-nibble fashion. The programmable interconnections are designed to provide fast hierarchical connections. To meet the challenge of implementing larger systems, the architecture supports system-level features such as a Programmable Clock Manager (PCM) and a microprocessor interface that can be used during and after the configuration.

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一种新型综合高效、高密度、高速的ORCA FPGA

本文介绍了一种新的ORCA FPGA，其重点是提高使用高级逻辑合成实现的逻辑系统的速度和门密度。在成功的ORCA系列(1C、2C、2CA和2TA)之后，新的ORCA系列被称为ORCA 3C/3T。除了常规的数字“逻辑”之外，该架构还设计用于有效地实现行为级“功能”。它包括查找表(LUTs)，触发器(ff)和一个pal类型的解码器块，以双咬方式分组。可编程互连的设计是为了提供快速的分层连接。为了应对实现更大系统的挑战，该体系结构支持系统级功能，例如可编程时钟管理器(PCM)和可在配置期间和配置后使用的微处理器接口。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of CICC 97 - Custom Integrated Circuits Conference

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