Reducing TLB power requirements

Abstract

Translation look-aside buffers (TLBs) are small caches to speed-up address translation in processors with virtual memory. This paper considers two issues: (1) a comparison of the power consumption of fully-associative, set-associative, and direct mapped TLBs for the same miss rate and (2) the proposal of modifications of the basic cells and of the structure of set-associative TLBs to reduce the power. The power evaluation is done using a model and the miss rates are obtained from simulations of the SPEC92 benchmark. With respect to (1) we conclude that for small TLBs (high miss rates) fully-associative TLBs consume less power but for larger TLBs (low miss rates) set-associative TLBs are better. Moreover, the proposed modifications produce significant reductions in power consumption. Our evaluations show a reduction of 40 to 60% compared to the best traditional TLB. The proposed TLB implementation produces an increase in delay and in area. However, these increases are tolerable because the cycle time is determined by the slower cache and because the TLB area corresponds to only a small portion of the chip area.