Developing cycle-accurate contract specifications for synchronous parallel-pipeline hardware: Application to verification

Abstract

The paper describes a methodology for formal cycle-accurate specification of synchronous parallel-pipeline hardware. The main application of the methodology is simulation-based verification of control-intensive digital designs. Its key features are as follows: (1) resources of a design under verification (buffers, arbiters, data transfer channels, etc.) are specified by means of reusable cycle-accurate models; (2) operations of a design (pipeline control flows) are described by defining contracts (i.e. pre- and post-conditions) for all operation stages (functional units of a pipeline). Formal specifications of that kind can be easily applied to automate simulation-based verification. The suggested solution is aimed at achieving technological effectiveness of specifications development.