A compact IDCT processor for HDTV applications

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI:10.1109/SIPS.1999.822320

Tian-Sheuan Chang, Jiun-In Guo, C. Jen

引用次数: 3

Abstract

This paper presents a compact IDCT processor for HDTV applications by using cyclic convolution and hardwired multipliers. By properly arranging the input sequence, we formulate IDCT into cyclic convolution that is regular and suitable for VLSI implementation. The hardwired multipliers that implement multiplications with scaled IDCT coefficients are optimized by common subexpression techniques. Based on these techniques, our proposed design costs 7504 gates plus 1024 bits of memory with 100M pixels/sec throughput.

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用于高清电视应用的紧凑型IDCT处理器

采用循环卷积和硬线乘法器，设计了一种适用于高清电视的紧凑IDCT处理器。通过对输入序列的合理安排，我们将IDCT转化为规则的、适合VLSI实现的循环卷积。通过公共子表达式技术对实现缩放IDCT系数乘法的硬连线乘法器进行了优化。基于这些技术，我们提出的设计成本为7504门加上1024位内存，吞吐量为100M像素/秒。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

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