{"title":"Design and implementation of a self-checking scheme for railway trackside systems","authors":"L. Schiano, C. Metra, Diego Marino","doi":"10.1109/MTDT.2002.1029763","DOIUrl":null,"url":null,"abstract":"We propose the self-checking design of the transmission and reception blocks of a trackside control system used for railway applications. Our scheme has been conceived for field-programmable gate arrays. A prototype has been implemented, whose correct operation has been verified by means of post-layout simulations and experimental measurements. Our scheme negligibly impacts system's performance and features self-checking ability with respect to a wide set of possible internal faults, representative of the most likely faults for FPGA-implemented systems.","PeriodicalId":230758,"journal":{"name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.2002.1029763","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
We propose the self-checking design of the transmission and reception blocks of a trackside control system used for railway applications. Our scheme has been conceived for field-programmable gate arrays. A prototype has been implemented, whose correct operation has been verified by means of post-layout simulations and experimental measurements. Our scheme negligibly impacts system's performance and features self-checking ability with respect to a wide set of possible internal faults, representative of the most likely faults for FPGA-implemented systems.
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