Carrier Dynamics in Lightly-doped Resistance Region in Power MOSFETs

Abstract

Two-dimensional current flow in the lightly-doped resistive region in a lateral double-diffused MOS (LDMOS) transistor was analyzed through 2D device simulation. While retaining its theoretical backbone of HiSIM_HV, the industry-standard surface-potential-based compact model for high-voltage MOSFETs, a conceptual extension is explored. Owing to a smooth transit of current flowlines from the channel to the lightly doped region adjacent to the channel of the intrinsic MOSFET part of LDMOS, the surface accumulation occurring at the gate-overlapped surface of the lightly doped resistive region is regarded as an extended channel rather than an extended drain. The channel offset length (ΔL) can be expressed within the framework of the drift-diffusion model and can be related with a characteristic quasi-Fermi voltage Vdive where accumulation current flowlines have already completely dived away from the surface. The HiSIM_HV’s internal drain node (DP or alternatively d’) is regarded as being placed at an opening bounded by the gate-controlled transverse and the drain-controlled lateral extension of depletion region, while many compact models place DP at the boundary between the channel and the lightly doped region. The intrinsic MOSFET’s effective drain voltage (Vdseff) is related to gate controlled Vdive rather than the quasi-Fermi voltage (Vdp) at DP. Hence, a difficulty in that the intrinsic MOSFET’s drain voltage stays almost as high as externally applied drain voltage at the off-state, while it suddenly drops at the onset of on-state of the intrinsic MOSFET part is expected to be mitigated.