Design of 3.3 V 10 bit current-mode folding/interpolating CMOS A/D converter with an arithmetic functionality

Abstract

A low power 10 bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent the ADC from increasing the FR excessively, but also to perform at high resolution with a single power supply of 3.3 V. The proposed ADC is implemented by a 0.6 /spl mu/m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of /spl plusmn/0.5 LSB, an integral nonlinearity (INL) of /spl plusmn/1.0 LSB.