Design and Implementation of Feed Forward Configurable Digital Power Limiter for On-Board Digital Processor

Abstract

Onboard digital processors are the emerging technological developments in the arena of satellite communication for its on-board flexibility, configurability and programmability. SSPAs (Solid State Power amplifiers) are common components in the RF chain of payloads. It can be sourced by multi carriers and can be driven into saturation by any of the individual carriers. Therefore, power limiter is required per channel for controlling the input power to SSPA from digital processor. Since the processor comprise of digital subsystems the work aims at a FPGA based design and development of feed-forward configurable power limiter having 30dB dynamic range. The architecture comprises of power detector, real time input maximum detector and input signal normalizing modules. It has two modes of operation: linear power mode and limiting power mode. It can be configured with thresholds from 0 dB to -5dB in steps of 0.5dB.