In-Depth Analysis of NBTI at 2X nm Node DRAM

Abstract

An analysis on the degradation of DRAM performance caused by the NBTI degradation of p-MOSFET is first to be reported. To improve the NBTI immunity, three candidates are examined. First, minimizing Si-H bonds at Si/SiON interface through controlling the heat-budget at BEOL shows a promising result in NBTI lifetime, but it is not appropriate for DRAM process since it decreases the refresh time. Next, the buried SiGe channel p-MOSFET, which has 1.2 times higher NBTI immunity, is considered but difficult to adopt in DRAM peripheral circuit due to extra manufacturing cost. Finally, a deuterium annealing seems to be the right candidate for DRAM process since it improves the NBTI immunity without the refresh time penalty. This NBTI gain, however, varies depending on the amount of deuterium atom at Si/SiON interface and the probability of Si-D bond replacement with Si-H bond. Thus, selecting a right process sequence and an annealing condition is crucial.