{"title":"Code sharing in CPLD-based Moore FSMs","authors":"A. Barkalov, L. Titarenko, J. Bieganowski","doi":"10.1109/MOCAST.2017.7937647","DOIUrl":null,"url":null,"abstract":"A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with CPLDs. The method is based on the idea of code sharing. The main difference from already known methods is that the counter increases its content during conditional and unconditional transitions. An example of application of proposed method is given.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MOCAST.2017.7937647","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A method of hardware reduction is proposed for logic circuits of Moore FSMs implemented with CPLDs. The method is based on the idea of code sharing. The main difference from already known methods is that the counter increases its content during conditional and unconditional transitions. An example of application of proposed method is given.
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