Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers

Abstract

Timing variation of sense amplifier enable (SAE) attributable to the random variation of transistor threshold Voltage is reduced by a novel Multi Replica Bitline Delay technique to provide the best tracking with process variations for SRAM applications. Multi replica bitline with a sufficient count of replica cells are utilized in parallel and delay of RBLs is added together to generate timing for sense amplifier (SA). Simulation results in IBM 65nm CMOS technology show that 50% timing variation is reduced at 1.0V supply Voltage.