Design of 1Gs/s open-loop Track-and-Hold for 10GBASE-T Ethernet receivers

Abstract

A 1Gs/s CMOS Track-and-Hold for the upcoming generation of Ethernet applications (10GBASE-T) is presented. The Track-and-Hold is designed to be employed as front-end in a time-interleaved analog-to-digital converter and it is based on an open-loop architecture composed of an input buffer and a highspeed switch. The proposed Track-and-Hold, designed in a 65nm low-power CMOS process, exhibits a total harmonic distortion lower than −80dB and a spurious free dynamic range better than 79dB, with a power consumption lower than 11mW (dual supply voltages 1.2V/2.5V, 1.85mA/4.22mA).