3D memory design based on through silicon vias enabled timing optimization

Xiaowei Chen, Seyed Alireza Pourbakhsh, L. Hou, Na Gong, Jinhui Wang
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Abstract

In three-dimensional (3D) integrated circuit (IC), a large number of dummy through silicon vias (TSV) are required for thermal and thinning concerns. However, limited attention is paid to the fact that these dummy TSVs can be multi-functional and used for timing purposes. In this paper, we propose to use those "timing wasteful" dummy TSVs to replace bit line delay cells. Also, a TSV allocation algorithm is presented to optimize the TSV array layout. Finally, three memory designs are implemented to verify the feasibility and reliability of the proposed technology. It is found that all delay cells in these 3 memories can be replaced by TSV arrays.
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基于硅通孔使能定时优化的三维存储器设计
在三维(3D)集成电路(IC)中,为了散热和减薄,需要大量的假导通硅孔(TSV)。然而,很少有人注意到这些虚拟tsv可以是多功能的,并用于定时目的。在本文中,我们建议使用这些“时间浪费”的虚拟tsv来取代位线延迟单元。同时,提出了一种TSV分配算法来优化TSV阵列布局。最后,通过三种存储器设计验证了所提技术的可行性和可靠性。发现这3种存储器中的延迟单元都可以用TSV阵列代替。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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