A 6.38 fJ/conversion 0.6V 0.43μW 100 kS/s 10-bit successive approximation ADC

Meng-Lieh Sheu, Cheng-Han Wu
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Abstract

This work presents a 10-bit successive approximation ADC for low voltage and low power applications. The chip operating voltage is 0.6 V with single-ended rail-to-rail swing input signal. Binary-weighted multilayer sandwich capacitor array is used in the digital to analog converter employed in the ADC to reduce the overall capacitance value and power consumption effectively. The proposed ADC is designed with 0.18 μm CMOS process. The simulation results at 0.6 V supply voltage, 100 kS/s sampling rate, and 1.38 kHz rail-to-rail swing input, an SNDR of 60.4 dB is achieved with 0.43 μW power consumption. The FOM is 6.38 fJ per conversion step.
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6.38 fJ/转换0.6V 0.43μW 100 kS/s 10位逐次逼近ADC
这项工作提出了一个适用于低电压和低功耗应用的10位连续近似ADC。芯片工作电压为0.6 V,单端轨对轨摆输入信号。在数模转换器中采用二值加权多层夹层电容阵列,有效地降低了整体电容值和功耗。该ADC采用0.18 μm CMOS工艺设计。仿真结果表明,在0.6 V供电电压、100 kS/s采样率、1.38 kHz轨对轨摆输入条件下,单信噪比为60.4 dB,功耗为0.43 μW。FOM为6.38 fJ每个转换步骤。
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