F. Roustaie, S. Quednau, F. Weissenborn, O. Birlem, David Riehl, Xiang Ding, Andreas Kramer, K. Hofmann
{"title":"Room Temperature KlettWelding Interconnect Technology for High Performance CMOS Logic","authors":"F. Roustaie, S. Quednau, F. Weissenborn, O. Birlem, David Riehl, Xiang Ding, Andreas Kramer, K. Hofmann","doi":"10.1109/ECTC32696.2021.00069","DOIUrl":null,"url":null,"abstract":"In this work we report a novel room temperature bonding technology based on metallic NanoWires, so-called KlettWelding. This technology can be used for bonding Flip-Chips with down to $5\\ \\mu\\mathrm{m}$ edge length bumps and fine pitches less than $8 \\mu\\mathrm{m}$. The process is expected to work for die to wafer (d2w) or wafer to wafer (w2w) bonding. The required bonding pressures range from 1 to 15 MPa for flip chips, Diodes, IGBT, MOSFETS, $\\mu \\mathrm{C}$, Video chips, LEDs and sensors. The measured shear strength of these connections yields 15 to 60 MPa. Such contacts have shown in the first results a high thermal conductance in the range of 350 W/mK. Also, the connections can tolerate temperatures higher than 500 °C.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC32696.2021.00069","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this work we report a novel room temperature bonding technology based on metallic NanoWires, so-called KlettWelding. This technology can be used for bonding Flip-Chips with down to $5\ \mu\mathrm{m}$ edge length bumps and fine pitches less than $8 \mu\mathrm{m}$. The process is expected to work for die to wafer (d2w) or wafer to wafer (w2w) bonding. The required bonding pressures range from 1 to 15 MPa for flip chips, Diodes, IGBT, MOSFETS, $\mu \mathrm{C}$, Video chips, LEDs and sensors. The measured shear strength of these connections yields 15 to 60 MPa. Such contacts have shown in the first results a high thermal conductance in the range of 350 W/mK. Also, the connections can tolerate temperatures higher than 500 °C.