Parameter space exploration for robust and high-performance n-channel and p-channel symmetric double-gate FinFETs

Abstract

The influence of different device parameters on the electrical characteristics of n-channel and p-channel symmetric double-gate FinFETs is studied in this paper. Guidelines for enhancing the performance and suppressing the leakage currents are provided. A sub-threshold slope lower than 100mV is achieved at the room temperature with fins thinner than half the gate length in a 32nm FinFET technology. The maximum on-current to leakage current ratio of n-channel FinFETs at room temperature is achieved when the fin thickness and the gate-oxide thickness are 8nm and 1.6nm, respectively. Alternatively, the on-current to leakage currents ratio of p-channel FinFETs is maximized when the fin thickness and the gate-oxide thickness are 8nm and 1.2nm, respectively.