{"title":"Building fast bundled data circuits with a specialized standard cell library","authors":"P. T. Røine","doi":"10.1109/ASYNC.1994.656302","DOIUrl":null,"url":null,"abstract":"A method for building fast, optimized bundled data circuits from a specialized CMOS standard cell library is presented. The method has been successfully used for the design of a FIFO buffer for a multicomputer network. This chip, which contains about 19000 transistors in a 1.5 /spl mu/m CMOS process, achieves a throughput of about 150 million symbols per second.","PeriodicalId":114048,"journal":{"name":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"90 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASYNC.1994.656302","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A method for building fast, optimized bundled data circuits from a specialized CMOS standard cell library is presented. The method has been successfully used for the design of a FIFO buffer for a multicomputer network. This chip, which contains about 19000 transistors in a 1.5 /spl mu/m CMOS process, achieves a throughput of about 150 million symbols per second.
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