{"title":"Discrete time large-signal model of dc-dc converters for system level simulation of digitally controlled SMPS","authors":"M. Meola, S. Carrato, G. Bernacchia, E. Bodano","doi":"10.1109/RME.2009.5201344","DOIUrl":null,"url":null,"abstract":"In this paper a new large-signal discrete time model for dc-dc converters is derived. The model is meant to overcome the lack of large-signal dc-dc converter models which, firstly, are able to accurately predict converter behavior in different operating modes and, secondly, can be implemented both in Matlab/SIMULINK and HDL language. The model is well suited to perform system level simulation of digitally controlled SMPS using synthesis tools targeted to FPGA and ASIC implementation and, therefore, avoiding time consuming mixedsignal simulations from the first stages of the design.","PeriodicalId":245992,"journal":{"name":"2009 Ph.D. Research in Microelectronics and Electronics","volume":"188 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Ph.D. Research in Microelectronics and Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RME.2009.5201344","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper a new large-signal discrete time model for dc-dc converters is derived. The model is meant to overcome the lack of large-signal dc-dc converter models which, firstly, are able to accurately predict converter behavior in different operating modes and, secondly, can be implemented both in Matlab/SIMULINK and HDL language. The model is well suited to perform system level simulation of digitally controlled SMPS using synthesis tools targeted to FPGA and ASIC implementation and, therefore, avoiding time consuming mixedsignal simulations from the first stages of the design.
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