{"title":"An Eight-core Class-G Switched-capacitor Power Amplifier with Eight Power Backoff Efficiency Peaks","authors":"Bo Qiao, A. V. Kayyil, D. Allstot","doi":"10.1109/RFIC54546.2022.9863094","DOIUrl":null,"url":null,"abstract":"An eight-core class-G polar switched-capacitor power amplifier (SCPA) is described that uses an eight-way digitally-scalable transformer (DST) and a new pseudo-differential class-G switch. Employing both supply and load modulation, eight seamless efficiency peaks are realized at 0 dB, 2.5, 6, 8.5, 12, 14.5, 18 and 24 dB power backoff levels by minimizing the dynamic switching loss in the capacitor array. A prototype chip was designed and fabricated in a 65nm CMOS process. It achieves peak output power and drain efficiency (DE) values of 27.2 dBm and 35.5%, respectively, at a carrier frequency of 2.42 GHz. Compared to a normalized class-B power amplifier, the measured DE is increased by $\\sim 3.3\\ \\mathrm{X}$. which corresponds to a 70% power saving. For a single-carrier 64 QAM signal with a 1 MHz bandwidth, the measured average output power and DE are 20.0 dBm and 23.1%, respectively, with an error vector magnitude (EVM) of −28.6 dB.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC54546.2022.9863094","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
An eight-core class-G polar switched-capacitor power amplifier (SCPA) is described that uses an eight-way digitally-scalable transformer (DST) and a new pseudo-differential class-G switch. Employing both supply and load modulation, eight seamless efficiency peaks are realized at 0 dB, 2.5, 6, 8.5, 12, 14.5, 18 and 24 dB power backoff levels by minimizing the dynamic switching loss in the capacitor array. A prototype chip was designed and fabricated in a 65nm CMOS process. It achieves peak output power and drain efficiency (DE) values of 27.2 dBm and 35.5%, respectively, at a carrier frequency of 2.42 GHz. Compared to a normalized class-B power amplifier, the measured DE is increased by $\sim 3.3\ \mathrm{X}$. which corresponds to a 70% power saving. For a single-carrier 64 QAM signal with a 1 MHz bandwidth, the measured average output power and DE are 20.0 dBm and 23.1%, respectively, with an error vector magnitude (EVM) of −28.6 dB.