Test quality for high level structural test

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940) Pub Date : 2004-11-10 DOI:10.1109/HLDVT.2004.1431250

Ahmad A. Al-Yamani, E. McCluskey

引用次数: 5

Abstract

Using complex (high-level) gates, such as multiplexers, full adders, etc., for automatic test pattern generation (ATPG) has several advantages. It makes A TPG faster and potentially reduces the size of the test set that needs to be applied. A variety of other techniques are used to reduce the size of test sets for digital chips. They typically rely on preserving the single-stuck-fault coverage of the test set. This paper presents data obtained from applying a variety of test sets on the ELF35 test chip and recording the test escapes. The data presented show the test quality effect of using complex gates as fault sites. The paper also shows the impact of test compaction and reduced fault coverage on the test quality.

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高水平结构试验质量

使用复杂(高级)门，如多路复用器、全加法器等，用于自动测试模式生成(ATPG)有几个优点。它使A TPG更快，并可能减少需要应用的测试集的大小。各种其他技术被用来减小数字芯片测试集的尺寸。它们通常依赖于保持测试集的单卡故障覆盖率。本文介绍了在ELF35测试芯片上应用各种测试装置并记录测试逃逸的数据。给出的数据表明，采用复杂栅极作为故障点对测试质量的影响。本文还展示了测试压实和降低故障覆盖率对测试质量的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)

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