{"title":"Programmable IF architecture for multi-standard software defined radios","authors":"F. Sheikh, S. Masud, A. Loan","doi":"10.1109/SIPS.2005.1579838","DOIUrl":null,"url":null,"abstract":"An improved intermediate frequency (IF) architecture for software defined radios is presented. This architecture is programmable, reconfigurable and suited to hardware implementation. The architecture is based on a computationally efficient method of extracting multiple channels belonging to two different communication standards, GSM and IS-95. The core of the system comprises of polyphase DFT filterbanks and very economical fractional rate-change filters. A flexible and efficient sample rate conversion method is also proposed that performs common rate changes using a shared hardware structure. Computational and hardware complexity comparisons are made based on results from a simulation test-bed developed for the proposed system.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2005.1579838","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
An improved intermediate frequency (IF) architecture for software defined radios is presented. This architecture is programmable, reconfigurable and suited to hardware implementation. The architecture is based on a computationally efficient method of extracting multiple channels belonging to two different communication standards, GSM and IS-95. The core of the system comprises of polyphase DFT filterbanks and very economical fractional rate-change filters. A flexible and efficient sample rate conversion method is also proposed that performs common rate changes using a shared hardware structure. Computational and hardware complexity comparisons are made based on results from a simulation test-bed developed for the proposed system.