{"title":"Automatic test pattern generation for sequential circuits using genetic algorithms","authors":"V. Rajesh, Ajai Jain","doi":"10.1109/ICVD.1998.646616","DOIUrl":null,"url":null,"abstract":"This paper discusses a new objective function to generate test patterns for sequential circuits using genetic algorithms. This approach is based on the importance of assigning a value (0 or 1) to a line with respect to faults in consideration. This is simulation based and can be used for any circuit that can be simulated logically.","PeriodicalId":139023,"journal":{"name":"Proceedings Eleventh International Conference on VLSI Design","volume":"106 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1998.646616","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
This paper discusses a new objective function to generate test patterns for sequential circuits using genetic algorithms. This approach is based on the importance of assigning a value (0 or 1) to a line with respect to faults in consideration. This is simulation based and can be used for any circuit that can be simulated logically.
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