A system design for real-time fault-tolerant computer networks

F. Shih, K. Nakajima
{"title":"A system design for real-time fault-tolerant computer networks","authors":"F. Shih, K. Nakajima","doi":"10.1109/HICSS.1989.47176","DOIUrl":null,"url":null,"abstract":"A system design that provides efficient self-testing and optimal real-time diagnosis for multiprocessor computer networks is presented. In this design, a test is performed by running a common system task on two processors and comparing their signal signatures, obtained from the data port and the control register. A simple diagnosis structure to be derived from a given system architecture is proposed. Optimal real-time diagnosis is achieved using a hardware accelerator based on the unit-diagnosis structure. The hardware used for both the comparison testing and the fault diagnosis are simple, sufficient, and suitable for real-time implementation. It is shown that the proposed design can be applied to most fault-tolerant architectures.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HICSS.1989.47176","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

A system design that provides efficient self-testing and optimal real-time diagnosis for multiprocessor computer networks is presented. In this design, a test is performed by running a common system task on two processors and comparing their signal signatures, obtained from the data port and the control register. A simple diagnosis structure to be derived from a given system architecture is proposed. Optimal real-time diagnosis is achieved using a hardware accelerator based on the unit-diagnosis structure. The hardware used for both the comparison testing and the fault diagnosis are simple, sufficient, and suitable for real-time implementation. It is shown that the proposed design can be applied to most fault-tolerant architectures.<>
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实时容错计算机网络系统设计
提出了一种多处理器计算机网络的高效自检测和最佳实时诊断系统设计。在本设计中,通过在两个处理器上运行一个共同的系统任务并比较它们从数据端口和控制寄存器获得的信号签名来执行测试。提出了一种从给定系统体系结构推导出的简单诊断结构。采用基于单元诊断结构的硬件加速器实现最优实时诊断。对比测试和故障诊断所使用的硬件简单、充足,适合实时实现。结果表明,所提出的设计可以应用于大多数容错体系结构。
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