Clock skew optimized VLSI architecture for zero frequency filter

Abstract

In today's world, mobile phones play an important role in communication. People using mobile phones often face the problem of noise signals affecting the quality of speech. Passive noise control suppresses the higher frequency acoustic noise. It is a technique that provides sound reduction by noise-isolating materials such as insulation, sound-absorbing tiles, or a muffler rather than a power source. In lower frequencies, passive techniques require material that is too bulky and heavy. So an alternative method called active noise cancellation that separates noise signal and speech signal is chosen. Zero frequency filter is a technique used for active noise cancellation of noisy speech signals. This filter is used for the characterization of glottal activity from speech signals thereby cancelling the noise. The main advantage of this method when compared to other noise cancellation methods is that noise need not be modeled separately. In this paper is to present the VLSI implementation architecture of zero frequency filter with useful clock skew optimization. This architecture can be used as voice processor in mobile applications. As clock frequency increases and the technology move towards sub-nanometer process, handling timing violations in the design becomes an increasingly complex and challenging task. Traditional approaches target for global zero skew in the process of timing closure costs in area and power and also limits the maximum achievable operating frequency. Useful clock skew optimization is an emerging technique that helps achieve timing closure. The work presented in this paper achieves timing closure with an area overhead of about 15.87% through useful clock skew optimization.