{"title":"A 65nm 1V to 0.5V linear regulator with ultra low quiescent current for mixed-signal ULV SoCs","authors":"G. de Streel, J. De Vos, D. Flandre, D. Bol","doi":"10.1109/FTFC.2014.6828597","DOIUrl":null,"url":null,"abstract":"A linear regulator for point of load power delivery with 280nA quiescent current and 0.008mm2 area is presented in this paper. Strong specifications on Power Supply Rejection Ratio (PSRR) and power consumption were included in the design at 0.5V output voltage to supply both low power analog and Ultra-Low-Voltage (ULV) digital circuits with a maximum load current of 0.5mA. Current mode pole splitting and NMOS source follower power stage allows us to optimize PSRR and guarantee stability whilst keeping low silicon footprint for the 6pf on-chip capacitor. We demonstrate its use for supplying a ULV CMOS imager that was manufactured in 65nm LP/GP CMOS process.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"304 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Faible Tension Faible Consommation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FTFC.2014.6828597","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
A linear regulator for point of load power delivery with 280nA quiescent current and 0.008mm2 area is presented in this paper. Strong specifications on Power Supply Rejection Ratio (PSRR) and power consumption were included in the design at 0.5V output voltage to supply both low power analog and Ultra-Low-Voltage (ULV) digital circuits with a maximum load current of 0.5mA. Current mode pole splitting and NMOS source follower power stage allows us to optimize PSRR and guarantee stability whilst keeping low silicon footprint for the 6pf on-chip capacitor. We demonstrate its use for supplying a ULV CMOS imager that was manufactured in 65nm LP/GP CMOS process.
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