Testing for resistive open defects in FPGAs

Abstract

This paper presents a new technique for detecting resistive open defects in FPGAs. This technique is based on the reconfigurability feature of FPGAs. Using this technique, the delay of a defective path is increased several times more than the delay of the fault-free path, resulting in a higher resolution in detectability of resistive open defects in FPGAs, even at lower tester speed. Various detailed SPICE simulations are performed to validate this method. Also, a test configuration generation scheme is presented for the entire FPGA.