A 130-μW, 64-channel spike-sorting DSP chip

Abstract

Spike sorting is an important processing step in various neuroscientific and clinical studies. An on-chip spike-sorting DSP must provide data-rate reduction while maintaining a power density much less than 800 μW/mm2. Most existing designs either provide only spike detection for multi-channel processing, or they provide detection and feature extraction only for a single channel. We demonstrate a chip for detection, alignment, and feature extraction simultaneously for 64 channels. Spike-sorting algorithms identified from a complexity-performance analysis are implemented on ASIC using a Matlab/Simulink-based architecture design framework. The chip has a modular architecture, which allows it to be configured to process 16, 32, 48, or 64 channels. Inactive cores are power-gated to reduce power consumption when the chip operates for less than 64 channels. The chip is implemented in a 90-nm CMOS process and has a power dissipation of 130 μW (power density of 30 μW/mm2) when processing all 64 channels. A data-rate reduction of 91.25% (11.71 Mbps to 1.02 Mbps) is achieved.