Transmitter equalizer training based on pilot signal and peak detection

Abstract

In high-speed communication systems, adaptive equalizers are widely applied to improve signal integrity in both master chip and slave chip. In this paper, a novel architecture with adaptive equalizers applied only in the master chip is proposed for the low-power design through adaptive equalizer trainings. Focused on the transmitter equalizer training, results show that proposed pilot signal/peak detection algorithm can dramatically improve the signal quality with small area and reasonable training time, but it has the limitation in canceling the inter-symbol interference caused by the pre-cursor of the channel.