Cylindrical Ru-SrTiO/sub 3/-Ru capacitor technology for 0.11 /spl mu/m generation DRAMs

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI:10.1109/VLSIT.2001.934938
C. M. Chu, M. Kiyotoshi, S. Niwa, J. Nakahira, K. Eguchi, S. Yamazaki, K. Tsunoda, M. Fukuda, T. Suzuki, M. Nakabayashi, H. Tomita, C. Shiah, D. Matsunaga, K. Hieda
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引用次数: 1

Abstract

We have developed a cylindrical Ru/ST/Ru capacitor for gigabit-scale DRAMs. Using cylindrical CVD-Ru as a storage node (SN), a new 2-step CVD-ST was employed to improve ST step coverage, surface morphology and to control composition at the Ru/ST interface. A SiO/sub 2/ equivalent thickness (t/sub eq/) of 0.6 nm and cell capacitance of 18 fF/cell with leakage current of 0.1 fA/cell at /spl plusmn/0.7 V applied voltage has been achieved on a 256K cylindrical Ru/ST/Ru capacitor array.
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用于0.11 /spl mu/m一代dram的圆柱形Ru-SrTiO/sub - 3/-Ru电容技术
我们开发了一种用于千兆级dram的圆柱形Ru/ST/Ru电容器。采用圆柱形CVD-Ru作为存储节点(SN)，采用一种新的两步CVD-ST来提高ST步的覆盖率、表面形貌和控制Ru/ST界面的成分。在256K圆柱形Ru/ST/Ru电容器阵列上，在/spl plusmn/0.7 V电压下，SiO/sub /等效厚度(t/sub eq/)为0.6 nm，电池电容为18 fF/cell，漏电流为0.1 fA/cell。
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2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)
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