System design verification leading to unprecedented quality

Abstract

The author focuses on systems design verification leading to unprecedented quality of ICs, ASICs, printed circuit boards and modules in systems. The Logic Modeling Group of Synopsys, Inc. provides simulation models so that customers get the ASICs right the first time in a systems environment. In addition to ASIC verification, Logic Modeling makes it possible for unprecedented quality of printed circuit board designs by getting the first or second revision of a board ready for manufacturing. Many of today's electronics companies spin boards three to five times and often change PLD or FPGA programs as many as seven to ten times. The only way to achieve real quality in the design process is to radically change the design verification methodology. Design verification needs to happen in the early stages of the design process before board prototyping or before ASIC fab.