A 0.115 /spl mu/m/sup 2/ 8F/sup 2/ DRAM working cell with LPRD (low parasitic resistance device) and poly metal gate technology for gigabit DRAM

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) Pub Date : 2001-06-12 DOI:10.1109/VLSIT.2001.934929
Hyunpil Noh, Woncheol Cho, G. Jeong, M. Huh, Jaemin Ahn, Y.S. Kim, Suock Jeong, Seongjoon Lee, Dongseok Kim, Hazoong Kim, J. Suh, Jinwon Park, Sang-Don Lee, H. Yoon
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引用次数: 0

Abstract

An 8F/sup 2/ stack DRAM cell, 0.115 /spl mu/m/sup 2/ in size, has been successfully integrated using a selective epitaxial plug scheme for landing plug contacts and poly metal gates and MIM COB capacitors, by which cell working has been proven under easy function check mode. The cell transistor exhibits sufficient saturation current (I/sub OP/) of >40 /spl mu/A with threshold voltage (V/sub tsat/) of 1.0 V.
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一个0.115 /spl mu/m/sup 2/ 8F/sup 2/ DRAM工作单元，采用LPRD(低寄生电阻器件)和多金属栅极技术用于千兆DRAM
一个8F/sup 2/堆叠DRAM单元，尺寸为0.115 /spl mu/m/sup 2/，已成功集成使用选择性外延插头方案，用于着陆插头触点和多金属门和MIM COB电容器，该单元已被证明在简单的功能检查模式下工作。在阈值电压(V/sub tsat/)为1.0 V的情况下，电池晶体管显示出足够的饱和电流(I/sub OP/)为bbb40 /spl mu/A。
本文章由计算机程序翻译，如有差异，请以英文原文为准。
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2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)
2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)
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