A 300MHz 10b time-interleaved pipelined-SAR ADC

Abstract

A 10bit 300MHz analog-to-digital converter is presented. It uses medium-resolution SAR ADC to replace low-resolution Flash ADC to solve the high power consumption problem. The structure of sharing the same residue amplifier in two channels can further reduce the power consumption and correct the gain error between different channels. The asynchronous clock generator for SAR comparator and the improved capacitor array structure help to decrease SAR ADC's decision time. Simulation results in 65nm shows that it could have ENOB of 9.1 bits at 300MHz sampling. And its power consumption is only about 15.4mW.