Jian-Hsing Lee, Yi-Hsun Wu, K. Peng, R. Chang, Talee Yu, T. Ong
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引用次数: 21
Abstract
Inserting the n-well and p+ diffusion into the drain region of NMOS transistor, the embedded SCR NMOS (ESCR NMOS), without changing any DC I-V characteristics of NMOS, and a very low capacitance (/spl sim/50 fF) ESD protection (LCESD) device are developed successfully for output pad and input pad, respectively. In addition, a protection scheme, combining the power protection device and a n+ guard-ring, is proposed and proven to be capable of protecting four directions ESD zapping and without increasing the LCESD device capacitance.
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