K. Seki, Kousuke Mikami, M. Baba, A. Katayama, H. Tanaka, Y. Hara, M. Kobayashi, N. Okada
{"title":"Single-chip FEC codec LSI using iterative CSOC decoder for 10 Gb/s long-haul optical transmission systems","authors":"K. Seki, Kousuke Mikami, M. Baba, A. Katayama, H. Tanaka, Y. Hara, M. Kobayashi, N. Okada","doi":"10.1109/CICC.2002.1012787","DOIUrl":null,"url":null,"abstract":"This paper describes a 10 Gb/s throughput FEC (Forward Error Correction) codec LSI for long-haul optical transmission systems. The FEC codec uses concatenated Reed-Solomon (255,239) and Convolutional Self Orthogonal Code (CSOC). In order to improve the error correction capability, the FEC code applies iterative CSOC decoding. As a result, the FEC codec provides 8.0 dB net coding gain at 1E-12 corrected bit error rate with 25% redundancy. Due to the low complexity of CSOC, the codec achieves a low power consumption of 3.59 W and a low gate count of 1.32 Mgates using 0.18 /spl mu/m CMOS technology.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"244 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012787","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
Abstract
This paper describes a 10 Gb/s throughput FEC (Forward Error Correction) codec LSI for long-haul optical transmission systems. The FEC codec uses concatenated Reed-Solomon (255,239) and Convolutional Self Orthogonal Code (CSOC). In order to improve the error correction capability, the FEC code applies iterative CSOC decoding. As a result, the FEC codec provides 8.0 dB net coding gain at 1E-12 corrected bit error rate with 25% redundancy. Due to the low complexity of CSOC, the codec achieves a low power consumption of 3.59 W and a low gate count of 1.32 Mgates using 0.18 /spl mu/m CMOS technology.
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