E. Baier, R. Clemen, W. Haug, W. Fischer, R. Mueller, W. Loehlein, H. Barsuhn
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引用次数: 3
Abstract
A 80ns 256K n-channel metal-gate DRAM with tour selectable data I/O buffers which permit the chip to be used as 64K×4, 128 × 2, or 256 × 1, with either parallel or serial data transfer at 20ns data rate, will be discussed.
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