Effect of oxide thickness on 32nm Pmosfet reliability

D. A. Hadi, S. Hatta, N. Soin
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引用次数: 3

Abstract

Negative Bias Temperature Instability (NBTI) has become one of the critical reliability concerns as scaling down CMOS technology especially on the pMOSFET device. A simulation study had been conducted on 32 nm conventional pMOSFET using the technology CAD (TCAD) Sentaurus Synopsys simulator tool. In this paper, the effects of the gate oxide thickness together with drain bias variations on the NBTI are studied. The effect on the device parameters such as interface traps concentration (Nit), threshold voltage (Vth) and drain current (Id) degradation had been investigated and explained in detail.
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氧化物厚度对32nm Pmosfet可靠性的影响
负偏置温度不稳定性(NBTI)已成为CMOS技术特别是pMOSFET器件的关键可靠性问题之一。利用senaurus Synopsys仿真工具对32 nm传统pMOSFET进行了仿真研究。本文研究了栅极氧化层厚度和漏极偏压变化对NBTI的影响。对界面阱浓度(Nit)、阈值电压(Vth)和漏极电流(Id)退化等器件参数的影响进行了详细的研究和解释。
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