A quadrature direct digital downconverter

P. Vancorenland, P. Coppejans, W. D. Cock, M. Steyaert
{"title":"A quadrature direct digital downconverter","authors":"P. Vancorenland, P. Coppejans, W. D. Cock, M. Steyaert","doi":"10.1109/CICC.2002.1012803","DOIUrl":null,"url":null,"abstract":"A quadrature direct digital down converter (DDD) is presented. The converter has a continuous time /spl Delta//spl Sigma/ noise shaping loopfilter with a quadrature bandpass characteristic. Through the integration of mixers in the AD converter, RF input signals in the range 0.3-1.6 GHz can be downconverted to a digital I and Q output stream at a bit rate of 128 MHz. The circuit is designed as a front-end for low power receivers with a 2 MHz wide IF bandwidth centered around 4 MHz. The converter, integrated in a 0.25 /spl mu/m CMOS technology, consumes 14 mW from a 2 V supply.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012803","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

A quadrature direct digital down converter (DDD) is presented. The converter has a continuous time /spl Delta//spl Sigma/ noise shaping loopfilter with a quadrature bandpass characteristic. Through the integration of mixers in the AD converter, RF input signals in the range 0.3-1.6 GHz can be downconverted to a digital I and Q output stream at a bit rate of 128 MHz. The circuit is designed as a front-end for low power receivers with a 2 MHz wide IF bandwidth centered around 4 MHz. The converter, integrated in a 0.25 /spl mu/m CMOS technology, consumes 14 mW from a 2 V supply.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
正交直接数字下变频器
提出了一种正交直接数字下变频(DDD)。转换器具有一个连续的时间/spl δ //spl σ /噪声整形环滤波器,具有正交带通特性。通过在AD转换器中集成混频器,可以将0.3-1.6 GHz范围内的射频输入信号以128 MHz的比特率下变频为数字I和Q输出流。该电路被设计为低功率接收器的前端,具有以4 MHz为中心的2 MHz宽中频带宽。转换器集成在0.25 /spl μ m CMOS技术中,从2v电源消耗14mw。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A signal integrity-driven buffer insertion technique for post-routing noise and delay optimization Modularized low temperature LNO/PZT/LNO ferroelectric capacitor-over-interconnect (COI) FeRAM for advanced SOC (ASOC) application SOI Hall effect sensor operating up to 270/spl deg/C A 402-output TFT-LCD driver IC with power-controlling function by selecting number of colors Understanding MOSFET mismatch for analog design
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1