{"title":"A 92.7% Peak Efficiency 48/1V DSD Power Converter with 102mV Droop and 1.6µs Settling Time for a 1A/10ns Load Transient","authors":"Yongchao Zhang, Zhuoqi Guo, Zhongming Xue, Zhuoneng Li, Xihao Liu, Shangzhou Zhao, Dexuan Lv, Mengqi Duan, Li Geng","doi":"10.1109/ICTA56932.2022.9963045","DOIUrl":null,"url":null,"abstract":"With the rapid growth of data centers, the power supply has shifted from 48/12/1V two-stage architecture to 48/1V single-stage. In this paper, a new two-phase sawtooth voltage mode PWM control is proposed for the double step-down (DSD) converter. In order to solve the problem of inherent cycle delay of PWM control, a fast-transient response scheme is proposed. The converter also has a precharge and soft start scheme, which is designed with a 0.18 µm BCD process. It achieves peak efficiencies of 92.7%, 90%, 87.8%, and 86% at 250 kHz, 500 kHz, 750 kHz, and 1 MHz, respectively. During a 1A/10 ns load jump, the undershoot is reduced from 200 mV to 102 mV and the setting time is reduced from 5.3 µs to 1.6 µs.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICTA56932.2022.9963045","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
With the rapid growth of data centers, the power supply has shifted from 48/12/1V two-stage architecture to 48/1V single-stage. In this paper, a new two-phase sawtooth voltage mode PWM control is proposed for the double step-down (DSD) converter. In order to solve the problem of inherent cycle delay of PWM control, a fast-transient response scheme is proposed. The converter also has a precharge and soft start scheme, which is designed with a 0.18 µm BCD process. It achieves peak efficiencies of 92.7%, 90%, 87.8%, and 86% at 250 kHz, 500 kHz, 750 kHz, and 1 MHz, respectively. During a 1A/10 ns load jump, the undershoot is reduced from 200 mV to 102 mV and the setting time is reduced from 5.3 µs to 1.6 µs.
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