Designing a 9.3μW Low-Power Time-to-Digital Converter (TDC) for a Time Assisted SAR ADC

Abstract

The Time-to-Digital Converter (TDC) is an impor-tant circuit block for digitally quantifying the time displacement between digital events. Among several applications of the TDC, this work focuses on its application to low-power Successive-approximation Analog-to-Digital Converters (SAR ADC). The TDC can assist the SAR algorithm to improve the energy efficiency of capacitive DAC switching schemes, which constitute a significant portion of the SAR ADC power dissipation. This work presents the design of a coarse 8-bit deep TDC in a manufacturable 28 nm Bulk CMOS technology, which displays good coverage of the SAR ADC input after a calibration step using tunable delay cells that were optimized for 0.6 V supply. In our design approach, we optimized for energy the sizing of the both delay cells and the LV registers. The TDC had a simulated mean power dissipation of just $9.25 \mu W$ at this voltage, making it a good candidate for applications that are not very demanding in terms of precision.