A 20ns 64K CMOS SRAM

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156700

O. Minato, T. Masuhara, T. Sasaki, Y. Sakai, T. Hayashida

引用次数: 34

Abstract

A 19.0mm264K×1 SRAM utilizing pulsed-word-line technique, P-well/bipolar technology, and 1.3μm gate MOS transistors, will be described. The RAM has typical address access time of 20ns and power dissipation of 70mW at 1 MHz cycle time.

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20ns 64K CMOS SRAM

将介绍利用脉冲字线技术、p阱/双极技术和1.3μm栅极MOS晶体管的19.0mm264K×1 SRAM。该RAM的典型地址访问时间为20ns，在1mhz周期时间下功耗为70mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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