Towards incorporating device parameter variations in timing analysis

Abstract

Presents a timing verification mechanism which finds the maximum true delay of the circuit and the combination of the device parameter variations/spl minus/caused by the imperfect fabrication process/spl minus/which produces this worst-case. The effect of device parameter variations is captured to produce correlated component delay models. These delay models are then incorporated into an accurate analysis approach involving timed path sensitization expressions and device parameter space exploration to find the worst-case instance.<>