A high efficiency wide-load-range asynchronous boost converter with time-based dual-mode control for SSD applications

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2016-11-01 DOI:10.1109/ASSCC.2016.7844123

Kyoungjin Lee, Haneul Kim, Jehyung Yoon, Hyoung-Seok Oh, Byeong-ha Park, Hojin Park, Yoonmyung Lee

引用次数: 5

Abstract

A highly integrated, high-voltage dual-mode boost converter is presented for solid-state drive (SSD) applications, where standby mode efficiency with < 500 μA load is as critical as active mode efficiency with > 100 mA load. To enhance efficiency in light load condition and to achieve wide operation load range, loss minimization by balancing conduction and switching loss is adopted and dynamic power gating scheme is applied for PFM mode operation. Moreover, robust dual mode operation is implemented with time-based control scheme, which enables operation with lower peak current for optimal loss balancing. The proposed converter is fabricated in 130 nm CMOS process with an area of 1.7 mm2. The measured efficiency for supplying 12 V output from 5.5 V input is 91% at its peak and 85% with extremely light load of 200 μA. It also achieves wide load range of 34.6 dB for > 85% efficiency and 18.8 dB for > 90% efficiency.

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

一种高效率、宽负载范围的异步升压变换器，具有基于时间的双模式控制，适用于固态硬盘应用

针对固态硬盘(SSD)应用，提出了一种高集成度高压双模升压转换器，在这种情况下，< 500 μA负载的待机模式效率与> 100 mA负载的主动模式效率同样重要。为了提高轻载工况下的效率，实现更宽的运行负载范围，采用平衡导通和开关损耗的最小化方法，并采用动态功率门控方案进行PFM模式运行。此外，采用基于时间的控制方案实现鲁棒双模式运行，使其能够在较低的峰值电流下运行，以达到最佳的损耗平衡。该转换器采用130 nm CMOS工艺制作，面积为1.7 mm2。在5.5 V输入提供12v输出的峰值效率为91%，在200 μA的极轻负载下效率为85%。它还实现了宽负载范围34.6 dB > 85%的效率和18.8 dB > 90%的效率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)

自引率

0.00%

发文量

期刊最新文献

Copyright page Fractional-N DPLL based low power clocking architecture for 1–14 Gb/s multi-standard transmitter A 16–43 GHz low-noise amplifer with 2.5–4.0 dB noise figure A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS A low-power calibration-free fractional-N digital PLL with high linear phase interpolator