J. Thomson, Bevan Baas, Elizabeth M Cooper, J. Gilbert, George Hsieh, P. Husted, Aparna Lokanathan, Jeffrey S Kuskin, David Mccracken, Bill Mcfarland, Teresa H Meng, D. Nakahira, S. Ng, Mahesh Rattehalli, Jeff L Smith, Ravi Subramanian, Lars Thon, Yi-Hsiu Wang, Robert Yu, Xiaoru Zhang, P. Cole, K. Hanley, D. Jianto, L. Johnson, C. Khan, S. Lee, S. Montoya, S. Padnos, A. Rabii, S. Tehrani, J. Wong, Zheng
{"title":"An integrated 802.11a baseband and MAC processor","authors":"J. Thomson, Bevan Baas, Elizabeth M Cooper, J. Gilbert, George Hsieh, P. Husted, Aparna Lokanathan, Jeffrey S Kuskin, David Mccracken, Bill Mcfarland, Teresa H Meng, D. Nakahira, S. Ng, Mahesh Rattehalli, Jeff L Smith, Ravi Subramanian, Lars Thon, Yi-Hsiu Wang, Robert Yu, Xiaoru Zhang, P. Cole, K. Hanley, D. Jianto, L. Johnson, C. Khan, S. Lee, S. Montoya, S. Padnos, A. Rabii, S. Tehrani, J. Wong, Zheng","doi":"10.1109/ISSCC.2002.992137","DOIUrl":null,"url":null,"abstract":"An 0.25 /spl mu/m CMOS mixed-signal baseband and MAC processor for the IEEE 802.11a WLAN standard in 0.25 /spl mu/m CMOS occupies 6.8/spl times/6.8 mm/sup 2/ and contains 4.0M transistors in a 196-pin BGA package. Power consumption for transmit and receive is 326 mW and 452 mW. Additional data rates up to 108 Mb/s are supported. The MAC is implemented using dedicated control and datapath logic, and includes registers that allow host software to configure and control its operation. This yields an overall design that is compact, power-efficient, and requires no off-chip RAM or program storage, yet is very flexible.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"111","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.992137","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 111
Abstract
An 0.25 /spl mu/m CMOS mixed-signal baseband and MAC processor for the IEEE 802.11a WLAN standard in 0.25 /spl mu/m CMOS occupies 6.8/spl times/6.8 mm/sup 2/ and contains 4.0M transistors in a 196-pin BGA package. Power consumption for transmit and receive is 326 mW and 452 mW. Additional data rates up to 108 Mb/s are supported. The MAC is implemented using dedicated control and datapath logic, and includes registers that allow host software to configure and control its operation. This yields an overall design that is compact, power-efficient, and requires no off-chip RAM or program storage, yet is very flexible.
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