K. Deng, Ming-Da Tsai, Chin-Shen Lin, Kun-You Lin, Huei Wang, S.H. Wang, W. Lien, G.J. Chem
{"title":"A Ku-band CMOS low-noise amplifier","authors":"K. Deng, Ming-Da Tsai, Chin-Shen Lin, Kun-You Lin, Huei Wang, S.H. Wang, W. Lien, G.J. Chem","doi":"10.1109/RFIT.2005.1598906","DOIUrl":null,"url":null,"abstract":"A Ku-band monolithic low-noise amplifier is presented in this paper. This LNA fabricated in commercial 0.18-/spl mu/m CMOS technology is a two-stage common-source design instead of cascode configuration for lower noise performance. This CMOS LNA demonstrates a gain of better than 10 dB and a NF of better than 3.2 dB from 14 to 15 GHz. The measured output P/sub 1dB/ is about 5.2 dBm and input IP3 is 1.6 dBm. The chip size including all testing pads is 0.88 /spl times/ 0.77 mm/sup 2/.","PeriodicalId":337918,"journal":{"name":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International Wkshp on Radio-Frequency Integration Technology: Integrated Circuits for Wideband Comm & Wireless Sensor Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT.2005.1598906","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 24
Abstract
A Ku-band monolithic low-noise amplifier is presented in this paper. This LNA fabricated in commercial 0.18-/spl mu/m CMOS technology is a two-stage common-source design instead of cascode configuration for lower noise performance. This CMOS LNA demonstrates a gain of better than 10 dB and a NF of better than 3.2 dB from 14 to 15 GHz. The measured output P/sub 1dB/ is about 5.2 dBm and input IP3 is 1.6 dBm. The chip size including all testing pads is 0.88 /spl times/ 0.77 mm/sup 2/.