FinFET-based Low-Power Approximate Multiplier for Neural Network Hardware Accelerator

Abstract

Approximate computing is a novel method in the field of designing hardware circuits and software algorithms. In some applications where approximate results and close to exact results are sufficient for our purposes, approximate computing can be used to reduce the circuit design costs to achieve higher accuracy. This paper proposes two new approximate multipliers based on approximate compressors. In proposed multipliers, NAND gates are used to generate the partial products, and we used the DUAL technique to normalize partial products at the compress level. FinFET 7nm technology is used to design the multipliers circuits and are simulated using HSPICE tool. Moreover, MATLAB evaluated the proposed multipliers in the neural network applications. According to the results, hardware parameters such as power consumption, delay, and area overhead have been optimized in the proposed multipliers compared to other designs. Also, higher accuracy in the applications of neural networks has been achieved. In the comparison to the state of the art counterparts, first proposed multiplier improved accuracy by 0.8%, and second multiplier, improved accuracy by 1%. Also, the delay and power consumption improved up to 15% and 44% respectively.