Automatic Verification Platform Based on RISC-V Architecture Microprocessor

Abstract

As the scale of microprocessor chips and its design complexity continues to increase, the verification becomes more and more difficult. The microprocessor is the core component of computer system, and the instruction set of which is an important cornerstone for building the basic software and hardware ecosystem. The instruction set is a set of specifications for translating program language into machine language, and is the interface of software and hardware collaboration. This paper proposes an automatic, hierarchical verification platform and gives the verification results of the RISC-V base instruction. For the call of different instructions, only the top-level module name corresponding to the call needs to be changed.