A low cost high performance register-controlled digital DLL for 1 Gbps/spl times/32 DDR SDRAM

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221227

Jong-Tae Kwak, Chang-Ki Kwon, Kwan-Weon Kim, Seong-Hoon Lee, J. Kih

引用次数: 37

Abstract

A low cost high performance register-controlled digital delay-locked loop (DLL) that has novel resolution-enhancing structure with inherent duty cycle correction capability was developed for 1 Gbps/spl times/32 DDR SDRAM. Experimental results in a 0.13 /spl mu/m 4 M/spl times/32 DDR SDRAM show <25 ps peak-to-peak jitter with quiet supply,

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一种低成本高性能的寄存器控制数字DLL，用于1gbps /spl次/ 32ddr SDRAM

针对1 Gbps/spl次/32 DDR SDRAM，开发了一种低成本高性能的寄存器控制数字锁滞环(DLL)，该DLL具有新颖的分辨率增强结构和固有的占空比校正能力。实验结果表明，在0.13 /spl mu/m 4 m /spl times/32 DDR SDRAM中，安静供电时的峰对峰抖动<25 ps，外部负载误差

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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