Towards cube-sized compute nodes: Advanced packaging concepts enabling extreme 3D integration

2017 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2017-12-01 DOI:10.1109/IEDM.2017.8268322
T. Brunschwiler, G. Schlottig, A. Sridhar, P. Bezerra, P. Ruch, N. Ebejer, H. Oppermann, J. Kleff, W. Steller, M. Jatlaoui, F. Voiron, Z. Pavlović, P. McCloskey, D. Bremner, P. Parida, F. Krismer, J. Kolar, B. Michel
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引用次数: 9

Abstract

Novel heat removal and power delivery topologies are required to enable ‘extreme 3D integration’ with cube-sized compute nodes. Therefore, a technology roadmap is presented supporting memory-on-logic and logic-on-logic in the medium and long-term, by (i) dual-side cooling and integrated voltage regulators, and (ii) interlayer cooling and electrochemical power delivery.
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面向立方体大小的计算节点:先进的封装概念实现了极致的3D集成
为了实现与立方体大小的计算节点的“极端3D集成”，需要新颖的散热和供电拓扑。因此，本文提出了一项技术路线图，通过(i)双面冷却和集成稳压器，以及(ii)层间冷却和电化学供电，在中长期内支持逻辑上的存储和逻辑上的逻辑。
本文章由计算机程序翻译，如有差异，请以英文原文为准。
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2017 IEEE International Electron Devices Meeting (IEDM)
2017 IEEE International Electron Devices Meeting (IEDM)
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