P. Blomme, J. Versluis, M. Ercken, Laurent Sourieau, H. Hody, G. Vecchio, V. Paraschiv, C. L. Tan, G. Van den bosch, J. van Houdt
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引用次数: 0
Abstract
We look at the challenges for scaling planar NAND flash for sub-15nm nodes, and show the implementation of hybrid poly\metal floating gate (FG), HfAlO based IGD, junctionless array, WL trimming, and EUV spacer defined double patterning in a fully planar NAND Flash array with good programming performance.