{"title":"Evaluation of multi-layered gate design on GME-TRC MOSFET for wireless applications","authors":"P. Malik, R. Chaujar, Mridula Gupta, R. Gupta","doi":"10.1109/SMELEC.2010.5549492","DOIUrl":null,"url":null,"abstract":"In this paper, the impact of multi-layered gate design assimilation on Gate Material Engineered Trapezoidal Recessed Channel (GME-TRC) MOSFET has been studied for wireless applications in terms of linearity performance metrics, using device simulators: ATLAS and DEVEDIT, and compared with conventional Trapezoidal Recessed channel (TRC) and GME-TRC MOSFETs. Simulation study reveals that GME-TRC MOSFET with Multi-Layered Gate implementation significantly enhances the linearity performance in comparison with conventional TRC-MOSFET and GME-TRC MOSFET in terms of figure of merit (FOM) metrics: VIP2, VIP3, IIP3 and higher order transconductance coefficients: gm1, gm2, gm3, thus proving its efficacy for high performance wireless applications.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMELEC.2010.5549492","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, the impact of multi-layered gate design assimilation on Gate Material Engineered Trapezoidal Recessed Channel (GME-TRC) MOSFET has been studied for wireless applications in terms of linearity performance metrics, using device simulators: ATLAS and DEVEDIT, and compared with conventional Trapezoidal Recessed channel (TRC) and GME-TRC MOSFETs. Simulation study reveals that GME-TRC MOSFET with Multi-Layered Gate implementation significantly enhances the linearity performance in comparison with conventional TRC-MOSFET and GME-TRC MOSFET in terms of figure of merit (FOM) metrics: VIP2, VIP3, IIP3 and higher order transconductance coefficients: gm1, gm2, gm3, thus proving its efficacy for high performance wireless applications.
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